1. Field of the Invention
The present invention relates to a semiconductor device in which warping is suppressed in a low wafer state and a manufacturing method thereof.
2. Description of the Related Art
A typical semiconductor device structure that is referred to as a chip size package (CSP), and a manufacturing method thereof are described in Japanese Patent No. 3455762. In the semiconductor device described in this prior patent reference, a plurality of wirings is provided on the top surface of an insulating film provided on a semiconductor substrate, columnar electrodes are provided on the top surfaces of connection pad sections of the wirings, and a sealing film is provided on the top surface of the insulating film including the wirings such that the top surface of the sealing film is flush with the top surfaces of the columnar electrodes.
In this instance, to prevent the exposure of the upper section of the peripheral surface and the bottom surface of the semiconductor substrate, the upper section of the peripheral surface of the semiconductor substrate is covered with a sealing film, and the bottom surface of the semiconductor substrate is covered with a lower-layer protective film.
In the conventional manufacturing method of the semiconductor device described above, first, a semiconductor substrate in a wafer state (hereinafter, referred to as a semiconductor wafer) on top of which the insulating film, the wirings, and the columnar electrodes are formed is prepared. Next, the bottom surface of the semiconductor wafer is adhered to the top surface of a lower-layer insulating film provided on the top surface of a dicing tape with a release sheet therebetween.
Next, a groove having a predetermined width is formed by half-cutting between each semiconductor device formation area on the top surface side of the semiconductor wafer. A sealing film is then formed within the groove and on the top surface of the insulating film including the wirings such that the thickness of the sealing film is thicker than the height of the columnar electrodes. Next, the top surface side of the sealing film is ground, and after the top surfaces of the columnar electrodes are exposed, the top surface of the sealing film including the top surfaces of the columnar electrodes is planarized.
Next, the sealing film, the semiconductor wafer, and the lower-layer protective film are cut at the center of the groove in the width direction. A support tape is then adhered to the top surfaces of the sealing film and the columnar electrode. The dicing tape and the release sheet are then peeled. As a result, a semiconductor device is obtained that has a structure in which the upper section of the peripheral side surface of the semiconductor substrate is covered by the sealing film and the bottom surface of the semiconductor substrate is covered by the lower-layer protective film.
However, in the conventional manufacturing method of the semiconductor device described above, the sealing film is formed in the groove and on the top surface of the insulating film including the wirings after the groove is formed on the top surface side of the semiconductor wafer by half-cutting. In other words, the sealing film is formed in a state where the strength of the semiconductor wafer is weakened as a result of the groove being formed. Therefore, there is a problem that, when the sealing film made of thermosetting resin such as epoxy system resin is hardened, the semiconductor wafer is relatively significantly warped.